The present invention relates to an apparatus and method for eliminating dc offset in an ac circuit and, more particularly, to an apparatus and method which utilizes coordinate transformations and control loops to accomplish the foregoing.
DC offset is a problem that often occurs in ac electrical circuits. In particular, in an ac circuit that is subject to a dc offset, an ac voltage signal will fluctuate such that the sum of the positive and negative fluctuations within a particular period approximates a particular voltage value that is above or below zero. Accordingly, the ac voltage signal is said to be offset by that particular voltage value.
Several problems arise as a result of a dc offset in an ac electrical circuit. For example, in an electric motor that utilizes magnetic cores, the cores can become saturated by the magnetic fields caused by the circulating dc currents. Also, large amounts of unwanted dc current may be circulated through an ac electrical circuit in excess of, e.g., an electrical machine's or solid state component's allowable rating.
DC offsets may be caused naturally or may be man-made. Natural causes include the natural effect of the start up or initial period of a circuit that begins from zero current flow through the electrical components of the circuit to a steady state current flow through the circuit. During this initial period, the ac current flowing contains a dc offset. Since the decay of this offset has been found to follow a time-constant T=L/R, dc offset can persist over a long period in high-Q circuits where there is slow decay. Such long decay can, e.g., cause arcing in circuit breakers, unwanted dynamic forces in bus bars, and saturation of magnetic cores.
Man-made causes include improper matching of a modulation frequency with a fundamental voltage in inverters. In particular, when inverters are used to generate alternating voltages, a dc voltage is alternately switched between one of two or more voltage levels. This switching occurs at a frequency (referred to as the modulating frequency) that is higher than the fundamental voltage that the inverter is to produce. When the modulation frequency is other than an odd triplen of the fundamental voltage, the modulated signal includes unequal positive and negative voltages producing a dc offset voltage. Attempts have been made to use a synchronous modulating scheme to prevent creation of a signal having unequal positive and negative voltages. However, since the modulation frequency is now tied to the fundamental frequency of the motor frequency, which varies with drive speed, the carrier frequency must also vary in order to be synchronous with the modulation frequency. Such an arrangement has been found to reduce the effectiveness of electromagnetic interference filtering, and also reduces the response of the control loops, and increases the peak current that the inverter must provide.
In another example of a man-made cause, where a dc voltage supplied to a six-pulse inverter varies slightly in a periodic and/or a random fashion, the ac output of the inverter contains dc voltage which, in turn, can produce a sequentially recurring dc offset current. A traditional method for attempting to eliminate dc offset included filtering the fundamental frequency from the ac voltage signal leaving a signal representative of the dc offset. A problem arises in that filtering the fundamental frequency requires filters with large time constants resulting in very sluggish response.
Another attempt to alleviate dc offset is described in U.S. Pat. No. 5,407,027 in which an elevator control apparatus is disclosed as including a cancellation circuit which cancels dc offset voltage. The cancellation circuit has a current detector that, after the elevator arrives at a destination and the inverter is disabled, samples and stores the output signal of the current detector. Once the inverter is again operating, the stored output signal is then added to the current detector output signal supplied to a control circuit that controls the inverter. A major disadvantage of such an arrangement is that the cancellation circuit fails to correct the dc offset contained in the ac output signal of the inverter, as described above.